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08/01/2018 · For the specific realization of an algorithmic ADC described in this paper, ..

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The algorithmic ADC aims to measure the non-linear error of the raw pipelined ADC and compensate it by interpolation-based procedure in the digital domain.

The architecture includes a low power raw pipelined ADC and a high resolution algorithmic ADC.

For the specific realization of an algorithmic ADC described in this paper, a multiple residue mode amplifier is used to ensure different decision trajectories and provide valid calibration information.

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A 0.9V 92dB delta-sigmaaudio ADC and a 10MS/s 11-b algorithmic ADC were implemented todemonstrate the proposed design techniques.

MIMO Systems, Theory and Applications.
[5] Yantao Qiao, Songyu Yu, Pengcheng Su and Lijun Zhang, "Research on an Iterative Algorithm of LS Channel Estimation in MIMO OFDM Systems", IEEE Transactions on Broadcasting, vol.

As a result the pipelined ADC analog power can be dramatically reduced.
The architecture includes a low power raw pipelined ADC and a high resolution algorithmic ADC.

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In this paper a 4-bit algorithmic current mode Analog-to-Digital Converter (ADC) has been implemented. A vital component of this ADC is a current comparator. We have simulated three popular structures of current comparators that can be used to implement this ADC and compared their performance. The circuit has been implemented using 0. 18 ?m CMOS technology with a supply voltage of 1. 8V.

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    A programmable algorithmic ADC for low-power wireless applications

  • urn:nbn:se:kth:diva-14276 : A flexible algorithmic ADC …

    A flexible algorithmic ADC for wireless sensor nodes

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